The invention relates to phase-shift lithography, particularly useful for semiconductor device fabrication.
Semiconductor device speed may be increased and device supply-voltage/power dissipation may be reduced by decreasing transistor threshold voltages, gate oxide thicknesses and/or transistor feature size. Such modifications have reduced the supply voltage of a 0.25 xcexcm technology chip operating at approximately 100 MHz to only about 1.0 V.
Improvements to lithographic methods provide an avenue for transistor feature size reduction. For cost efficiency it is particularly desirable to reduce feature size using existing lithography tools. Currently, certain wavelength lithography tools are more widely used than others. Therefore, it is preferable to implement lithography techniques using the more common tools.
Alternating phase-shift masks used in photolithography methods have been implemented to enable reduction in feature size by decreasing diffraction effects and thus increasing resolution. The mask imparts a phase-shift to the incident radiation, typically by xcfx80 radians for a portion of the mask pattern. By providing adjacent mask pattern features with different phases from one another, diffracted regions may be canceled, thereby improving resolution.
Another approach to enabling feature size reduction, and consequently increasing device speed and reducing supply-voltage requirements and power dissipation, is the use of dual-mask processes. In a dual-mask process a phase-shift mask is used to image features that, because of their dimensions and/or positions, benefit from the mask""s resolution enhancing capabilities. A second mask, typically a binary mask, is used to trim unwanted phase boundaries by double-exposing those areas.
To further increase device speed and reduce supply-voltage and power dissipation, low threshold voltage channel PMOS transistors have been fabricated using a WSi/WSiN/Poly:Si (n+/p+) gate electrode stack. The stack helps prevent boron lateral diffusion to enable fabrication of the low-threshold voltage transistors. Reduced feature size devices using this technology, have resulted in digital signal processors having improved speed and a reduced supply voltage.
It is desirable to increase device speed and decrease supply-voltage and power dissipation beyond what is described above to further improve device performance. It is also desirable to do so using existing manufacturing tools. It is particularly desirable to enhance the speed of digital signal processors which are currently the computing engines of choice for low-cost, low-power applications such as telecommunications.
A multi-mask, strong phase-shift lithographic process is used to fabricate a digital signal processor capable of operating at 100 MHz with a 1.0 volt power supply.
In an illustrative embodiment of the invention a first exposure is made through a dark field phase-shift mask to define a first portion of the gate electrode, and a second exposure is performed through a binary bright field mask to shadow the first portion of the gate electrode and define a second portion of the gate electrode. This two-mask exposure process simplifies phase shifting and assists in scaling down gate lengths.
In a further embodiment of the invention a n+/p+ dual-Poly:Si module, and dopant penetration suppression techniques are utilized to attain the desired operating frequency and power.
Further disclosed is a digital signal processor comprising one or more components fabricated according to the method.